Integrated circuits (ICs) are utilized today in many areas including those not associated with the computer industry. These integrated circuits are usually produced by a fabrication process, such as metal-oxide semiconductor fabrication. Due to the importance of the proper functioning of these devices, it is essential that comprehensive testing be performed when they are being mass produced to ensure that each of the ICs performs as designed and is as fault and error free as possible. Therefore, every chip is tested during production to determine whether defects in the microelectronic circuit elements fabricated in the device will adversely affect the performance of the device.
Since ICs are so widely used, the overhead in terms of testing costs and man hours is a serious concern of the semiconductor manufacturer. For simple chip designs, it is a simple matter to test the chip as a whole. Obviously, as chip designs become more complex, the physical overhead and time required for testing can contribute enormously to the overall cost of the devices. In testing a chip, a set of test inputs, commonly referred to as test vectors, are developed and applied to the inputs of the device. If the chip is in good condition, the chip will produce results in response to these test vectors which will match a set of expected results.
Prior art IC testers are categorized as either single site testers or multi-site testers. Single site testers test one device at a time, while multi-site testers test multiple devices at the same time. A single site tester is shown in FIG. 1. Referring to FIG. 1, the single site tester 100 usually comprises a processor 101 and multiple resources coupled to a bus 102. Processor 101 controls the operation of the tester. The resources are typically memory 103, input/output peripherals 104, power supplies 105, power management resources 106 and a pattern generator 107. Pattern generator 107 provides the test vectors to the device under test (DUT) 108 (i.e., the device which is currently being tested). DUT 108 is normally either a memory device, processing device (e.g., a microprocessor), a sub-controller device or other integrated circuit device that requires testing.
The resources that are required for use in testing an IC are application specific. Each specific integrated circuit design may require different amounts of these resources. For example, to provide the necessary test vectors, the memory resources available to a processor in a tester may have to be increased. Therefore, a tester must be designed so that it can provide all the resources that are required in testing of the device (i.e., the chip). Also note that in a single site tester, a single processor controls the supply of the test vectors. It is possible with such a configuration to test multiple devices at the same time where all are running the same processes. However, the single processor must have the capability of determining which DUTs pass or fail the test criteria. In prior art, it is also possible for a single vector sub-controller to test multiple devices (DUTs) at a time even with different DUT pin counts and DUT functionality assuming the test vectors are linear in execution (i.e., no loops, branches, etc.). However, testers of the prior art are not hardware configured to accept devices which require only 63 pins, 22 pins or other numbers of pins at the same time. The testers of the prior art must have partitions that are the same size (i.e., pin groupings which are the same size). It is desirable to be able to test devices having different pin counts at the same time.
With multi-site testers, multiple ICs may be tested at the same time by placing each IC in a different site. Note that in a multi-site tester, resources are allocated to each site. Because each site must be able to accommodate different ICs, each site must be allocated with the maximum amount of resources that would be needed to provide testing for every possible IC that may be tested. If some of the resources are not utilized during the testing of a particular IC, then those resources are, in effect, wasted. It would be desirable to provide a testing environment in which the sites of the tester can be allocated with only those resources that are required to complete the testing. Note that this problem exists in other prior art testing configurations. For instance, in one prior art tester embodiment, each pin is allocated a predetermined number of dedicated resources. As with the multi-site tester, these resources are often not fully utilized, thereby wasting those unused resources.
Note that in a multi-site tester, one processor controls the testing operation for all the sites. In other words, one processor acts as the master for the system. The master/slave relationship between one control element and the other control elements in a system is also found in computer systems in which resources are shared. A typical prior art system is shown in FIG. 2 wherein processor 201 has access to a set of resources 202. Resources 202 would typically include at least memory and I/O facilities. Resources 202 are shared with another processor 203, which is often a digital signal processor in prior art computer system configurations. In such a system, processor 201 controls the resources and shuts off or prevents processor 203 from accessing the resources when processor 201 is using them.
Node-based computer systems have the same limitations. In the parallel processing environment of a node based system, if a task is being performed by a processing element and that processing element does not have enough resources, then a sub-task is formed. The sub-task has it own dedicated set of resources of which the processing element of the main task does not have access. An example of such a system is shown in FIG. 3. Referring to FIG. 3, multiprocessing elements 301-304 are coupled to one another. For example, processing element 301 is coupled to processing elements 302 and 304 and processing element 304 is coupled to processing elements 305-307. Each of processing elements 301-309 has its own set of dedicated resources. In the system of FIG. 3, Task A is given to processing element 301 for execution. In performing Task A, processing element 301 determines that additional resources are required, so sub-task 1 is formed and sent to processing element 304 for completion. Similarly, if sub-task 1 requires additional resources, another sub-task (e.g., sub-task 2), is formed and sent to one of the processing element, such as processing element 305, for completion. If Task A is an independent process that does not require sub-task 1 for completion, then the two tasks can be performed in parallel. If Task A is not an independent process, then it must wait for sub-task 1 to be completed. In any case, the only accesses Task A has over the resources utilized by sub-task 1 is by sending a task to be completed to sub-task 1. The same is true when sending a sub-task, such as that sent to processing element 305. It is desirable to have more than one task being accomplished at the same time and still have some control over the resources.
The present invention provides a computer system which allows the resources to be utilized by more than one processing element while performing more than one task at one time. The present invention also provides a multi-site testing arrangement in which the resources are not dedicated to one site, such that resources may be allocated to processes that require them. In this manner, the present invention provides a multi-site integrated circuit tester which utilizes the resources more efficiently.